1. Field of the Invention
The present invention generally relates to a fabrication technique for Complementary Metal-Oxide-Semiconductor (CMOS) devices. Particularly, the present invention relates to a method for fabricating silicide shunt for use in dual-gate CMOS device having a barrier layer effectively retarding lateral dopant diffusion.
2. Technical Background
In the structural configuration of a dual-gate CMOS device, a PMOS and a NMOS employing P-type impurities-doped polysilicon layer and N-type impurities-doped polysilicon layer as gates thereof, respectively, have been proposed for sub-quarter micro VLSI fabrication. Owing to the utilization of a P-type polysilicon gate, a threshold-voltage adjustment implantation, usually, by boron ion, for P-MOSFET can be left out, which not only makes P-MOSFET less susceptible to the short channel effect, but also easily optimizes the electrical characteristics of both of NMOS and PMOS devices in symmetry.
Under some circumstances, while the gates of the NMOS and PMOS devices should be connected to each other, it means that the P-type polysilicon gate and N-type polysilicon gate should be joined together. However, a good ohmic contact can not be attained if the polysilicon gates with reverse conductivity types, N-type and P-type, directly come into contact with each other, because of a P-N junction built therebetween. Therefore, a silicide layer is usually provided to form over the P-type and N-type polysilicon gates in parallel serving as a silicide shunt for ensuring the ohmic contact between them. Unfortunately, through the silicide shunt, the fast lateral dopant diffusion between P-type and N-type polysilicon gates degrades the doped concentration and jeopardizes the electrical characteristics thereof. Consequently, a diffusion barrier layer formed within the silicide layer is proposed to retard the lateral dopant diffusion described below.
A conventional process for fabricating silicide shunt for use in a dual-gate CMOS device is shown in FIGS. 1A-1C in cross-sectional view, further accompanied by FIG. 2, a top-view drawing for detailed description. The conventional method is suited to a silicon substrate 1, as shown in FIG. 1A, having twin-well regions, such as a P-well region 100 and an N-well region 102. A oxide layer 104 is formed above the junction between the P-well region 100 and the N-well region 102, through the LOCOS (local oxidation of silicon) method, for isolating NMOS and PMOS devices formed in the P- and N-well region respectively. Then, oxidation to the portion not covered by the oxide layer 104 forms a gate oxide layer 10, about 90 .ANG. in thickness, over the P-well region 100 and the N-well region 102. Subsequently, a polysilicon layer 12, and a silicide layer 14, such as titanium or tungsten silicide, are formed to cover the gate oxide layer 10 and the oxide layer 104, wherein the portion of the silicide layer 14 above the P-well and N-well regions 100 and 102 are respectively implanted with N-type impurities, such as phosphorus, and P-type impurities, such as boron or BF.sub.2.sup.+ to form N-type silicide layer 141 and P-type silicide layer 142.
Next referring to FIG. 1B, a photoresist layer 106 with designated patterns is formed on the silicide layer 14 by a photolithography procedure. Through the masking of the photoresist layer 106, the silicide layers 141 and 142 as well as the polysilicon layer 12 are all etched and patterned to form an opening 108 to expose a portion of the oxide layer 104.
Then, the photoresist layer 106 is removed in the step depicted in FIG. 1C. Afterwards, a metal nitride layer 16, such as titanium nitride, is deposited onto the silicide layer 14 and the exposed portion of the oxide layer 104 through the opening 108 serving as a diffusion barrier layer. Furthermore, sequential processes for defining gate patterns, forming N-type source/drain regions 18 and P-type source/drain regions by two implantation procedures accomplish the structural configuration shown in FIG. 2, wherein the region 108 is the area of the opening 108 depicted in FIG. 1B.
However, the conventional method, especially in the step of depositing metal nitride layer 16 as the diffusion barrier layer, suffers from inferior step coverage while depositing the metal nitride layer filling into the opening 108 because of high height to width ratio therein. Moreover, in the procedure of defining the gate patterns, i.e., the etching to the metal nitride layer 16, the silicide layer 14, and the polysilicon layer 12 are required, and therefore the photoresist layer alone can not resist without another silicon oxide layer formed below the photoresist layer 106 as a hard mask. This increases the complexity of fabrication.